1. Field of the Invention
The present invention relates to a gate driver. More particularly, the present invention relates to a gate driver capable of providing a reliable output signal and a display device that employs the gate driver.
2. Description of the Related Art
Display devices for displaying an image by controlling pixels arranged in a matrix have been widely used. Examples of such display devices are liquid crystal display devices (LCD) and organic light emitting diode devices (OLED). Such display devices typically include a display panel having pixels arranged in a matrix, a gate driver for selectively providing a drive signal to rows of pixels on a line by line basis, and a data driver for providing drive signals to the pixels.
Display devices having a gate driver and/or a data driver embedded on the display panel have been developed. Such display devices attempt to achieve the advantages of a low manufacturing cost, a process simplification, lightness and slimness. When manufacturing the display panel, the gate diver and/or the data driver are/is concurrently manufactured. To this end, a plurality of thin film transistors (TFTs) are provided to control each of the pixels in the display panel, and the gate driver and/or the data driver can be manufactured through the same semiconductor process as the TFT.
The gate drivers of the display device typically include a plurality of shift registers for providing the requisite output signals used to drive individual rows of pixels. There may be a one-to-one correspondence between each gate line and driver. For example, when the display panel has ten gate lines, at least ten shift registers are provided to provide the corresponding output signals to the ten gate lines, respectively.
FIG. 1 is a block diagram of one embodiment of a known gate driver. As shown, the gate driver includes a plurality of shift registers SRC1 through SRC[N+1] connected in cascade to each other. In this cascade arrangement, the output terminal OUT of each shift register is connected to the set terminal SET of the next shift register. The shift registers include N shift registers SRC1 through SRC[N] corresponding to N gate lines, and a dummy shift register SRC[N+1] that is used to reset the last shift register SRC[N].
The first shift register SRC1 is set by a pulse start signal STV. The pulse start signal is synchronized with a vertical synchronization signal Vsync. Each of the shift registers SR2 through SRC[N+1] is set by the output signal of the immediately preceding shift register in the shift register sequence. When there are N gate lines, output signals GOUT1 through GOUT[N] of the shift registers are connected to the corresponding gate lines, and an output signal GOUT[N+1] of the dummy shift register SRC[N+1] is not connected to any gate line.
A first clock CKV is supplied to the odd-numbered shift registers SRC1, SRC3, . . . , and a second clock CKVB is supplied to the even-numbered shift registers SRC2, SRC4, . . . . Here, the phase of the first clock CKV is opposite to that of the second clock CKVB. The first clock CKV is connected to drive the odd-numbered shift registers SRC1, SRC3, . . . , and the second clock CKVB is connected to drive the even-numbered shift registers SRC2, SRC4, . . . . The pulse start signal STV is applied to the first shift register SRC1 when the second clock CKVB is high.
The shift registers SRC1 through SRC[N] provide the respective output signals GOUT1 through GOUT[N] in synchronization with the first clock CKV or the second clock CKVB. Each of the shift registers SRC1 through SRC[N] is reset by the output signal of the shift register that immediately follows it in the shift register sequence. However, since there is no shift register subsequent to the dummy shift register SRC[N+1], the dummy shift register SRC[N+1] is reset by its own output signal GOUT[N+1].
FIG. 2 is a circuit diagram of the first and second shift registers illustrated in FIG. 1, while FIG. 3 is a waveform diagram showing the signals used to drive the first shift register of FIG. 2. Since each of the shift registers illustrated in FIG. 1 is identical in structure with the other, only the first shift register SRC1 is described in connection with FIGS. 2 and 3 for convenience.
When the pulse start signal STV is high, the first clock CKV and the second clock CKVB are low and high, respectively. Referring to FIGS. 2 and 3, the first shift register SRC1 is set by a high state of the pulse start signal STV during a cycle of the second clock (CKVB) period. More particularly, when the pulse start signal STV is applied, a node Q is charged to the voltage of the pulse start signal STV. A first transistor M1 is turned on by the voltage of the node Q. The node QB is then discharged by the voltage difference (VDD−VSS) that exists between a first power supply voltage and a second power supply voltage. As a result, the node QB is driven to and maintained at a low voltage level corresponding to the ratio of a resistance Rl of the first transistor M1 and a resistance R6 of a sixth transistor M6.
During a first clock (CKV) period, the first output signal GOUTl is provided in response to the first clock CKV signal. More particularly, when the first clock CKV is applied to the second transistor M2, a voltage boost results from pumping the drain-gate capacitance Cgd of the second transistor M2. Thus, the node Q is charged to a voltage level that is higher than the voltage level of the charged pulse start signal STV. Accordingly, the second transistor M2 is turned on and the first clock CKV is provided as the first output signal GOUT1.
During the second clock (CKVB) period, the first shift register SRC1 is reset by the output signal GOUT2 of the next shift register SRC2 in the shift register sequence. More particularly, when the fifth transistor MS is turned on by the second output signal GOUT2 of the shift register SRC2, the node Q is discharged by the first power supply voltage VSS through the fifth transistor M5. Additionally, the first transistor M1 is driven to a nonconductive state by the voltage now found at node Q. The node QB is charged using the second supply voltage VDD connected to the node QB through the sixth transistor M6. This causes the third and fourth transistors M3 and M4 to enter a conductive state. Accordingly, node Q is discharged to the first supply voltage VSS through the conductive fourth transistor M4. In this case, most of the output signal GOUT1 is discharged through the source-drain path of the second transistor M2, and the remaining output signal GOUTl is discharged to the first power supply voltage VSS through the conductive third transistor M3.
However, an undesired output signal may be generated from each of the shift registers SRC1 through SRC[N] in this known gate driver arrangement. As illustrated in FIG. 4, when a gate drive signal GOUT[N] is provided from the Nth shift register SRC[N] by the second clock CKVB, spurious drive signals are also provided from the second and fourth output signals GOUT2 and GOUT4 as well as from all even-numbered shift registers SRC2 and SRC4 to which the second clock CKVB is applied. More particularly, in addition to the desired drive signal, a plurality of undesired drive signals may be provided during one clock period.
The shift registers SRC1 through SRC[N] output drive signals at the corresponding output GOUT1 through GOUT[N] once a frame. For example, the fourth shift register SRC4 provides the fourth output signal GOUT4 during a period of the second clock signal (CKVB), but does not output the drive signal during the remaining period (90%) of one frame. To drive the fourth shift register in this manner, the third transistor M3 of the fourth shift register SRC4 must be turned on and, thus, node QB, which is connected to the third transistor M3, always maintains a high state during the remaining frame period. When this operation is repeated for each frame, the third and fourth transistors M3 and M4 are degraded. Accordingly, the threshold voltages of the third and fourth transistors M3 and M4 are shifted and, thus, the transistors M3 and M4 cannot be readily driven to a non-conductive state. In serious cases, the fourth transistor M4 is not driven to a non-conductive state and, thus, node Q is not reset. The output signals from the shift register therefore provide spurious drive signals at undesired times in response to the first or second clock CKV or CKVB.
Taking this into consideration for all the shift registers SRC1 through SRC[N], when the sixth drive signal GOUT6 is provided from the sixth shift register SRC6 as a result of the second clock signal CKVB, spurious drive signals are also provided at the second and fourth outputs GOUT2 and GOUT4 as well as from each of the even-numbered shift registers SRC2, SRC4, SRC8, SRC10, . . . to which the second clock CKVB is applied. This causes the display device to malfunction (i.e., screen flickering, etc.) thereby degrading the reliability of the product.